The present invention relates, in general, to Phase-Locked Loop (PLL) devices and, more particularly, to the tuning of a digitally controlled Voltage-Controlled Oscillator (VCO) in a PLL.
Phase-Locked Loops (PLLs) are widely used for clock generation or synchronization in data local area networks, data storage applications, disc drives, microprocessors, and communication systems. The PLL in communication systems and computer systems generally includes a phase detector, a loop filter, a Voltage-Controlled Oscillator (VCO), and a loop frequency divider. The phase detector receives a reference clock signal and a loop clock signal and provides a phase detect output signal that indicates the phase difference between the loop clock signal and the reference clock signal. The phase detect output signal is transferred to an input of the loop filter for generating a filtered signal to the VCO. The filtered signal provides a voltage to the VCO that adjusts the phase and frequency of the VCO output signal. The VCO output signal is typically scaled to a lower frequency by the loop frequency divider in generating the loop clock signal for the phase detector.
When the loop clock signal produced by the VCO is synchronized to the reference clock signal, these two signals have the desired phase-frequency relationship and the PLL is locked. If the loop clock signal and the reference clock signal are out of phase, the voltage generated by the phase detector is applied to the VCO for changing the capacitance value of a tank circuit and the resonant frequency at which the tank circuit oscillates. The dynamic adjustments to the voltage supplied to the VCO correct the frequency of the clock output signal to regain phase and frequency lock.
Typically, the capacitive and inductive components associated with the tank circuit vary over a range of values and component trimming is required to achieve the desired tuning of the VCO. Whether the capacitive and inductive components are integrated or discrete components, component tolerances are compensated through trimming which allows the voltage supplied by the phase detector a tuning range that is sufficient for the VCO to achieve phase lock for the PLL. The trimming adjusts the capacitive and/or inductive components to center the oscillator frequency. A limited operating supply voltage also limits the tuning range and necessitates component trimming, increasing the manufacturing cost due to additional steps and testing.
One method of trimming is to utilize an up/down counter in connection with a comparator for determining whether the tank circuit should be further tuned. The up/down counter can be controlled via its clock signal in addition to its up/down control bits. Typically, the phase detector drives the clock signal with a phase-differenced clock or, alternatively, an independent fixed frequency device may drive the clock of the up/down counter. Although these methods work for most applications, they fail to enable the VCO to tune to a frequency fast enough for some applications due to inherent problems caused by a fixed clock or a clock dependent on the phase detector. Accordingly, it would be advantageous to have a PLL device and a method for improving the tuning speed of the VCO by providing a better solution for driving the clock of the up/down counter for assisting the VCO to reach its lock in a specified time frame, especially when the initial frequency difference is large.